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 SN74LS299 8-Bit Shift/Storage Register with 3-State Outputs
The SN74LS299 is an 8-Bit Universal Shift / Storage Register with 3-state outputs. Four modes of operation are possible: hold (store), shift left, shift right and load data. The parallel load inputs and flip-flop outputs are multiplexed to reduce the total number of package pins. Separate outputs are provided for flip-flops Q0 and Q7 to allow easy cascading. A separate active LOW Master Reset is used to reset the register.
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* Common I/O for Reduced Pin Count * Four Operation Modes: Shift Left, Shift Right, Load and Store * Separate Shift Right Serial Input and Shift Left Serial Input for Easy * * *
Cascading 3-State Outputs for Bus Oriented Applications Input Clamp Diodes Limit High-Speed Termination Effects ESD > 3500 Volts
20
LOW POWER SCHOTTKY
GUARANTEED OPERATING RANGES
Symbol VCC TA IOH IOL IOH IOL Parameter Supply Voltage Operating Ambient Temperature Range Output Current - High Q 0 , Q7 Output Current - Low Q 0 , Q7 Output Current - High I/O0 - 1/O7 Output Current - Low I/O0 - 1/O7 Min 4.75 0 Typ 5.0 25 Max 5.25 70 - 0.4 8.0 - 2.6 24 Unit V C mA mA mA mA
1
PLASTIC N SUFFIX CASE 738
20 1
SOIC DW SUFFIX CASE 751D
ORDERING INFORMATION
Device SN74LS299N SN74LS299DW Package 16 Pin DIP 16 Pin Shipping 1440 Units/Box 2500/Tape & Reel
(c) Semiconductor Components Industries, LLC, 1999
1
December, 1999 - Rev. 6
Publication Order Number: SN74LS299/D
SN74LS299
CONNECTION DIAGRAM DIP (TOP VIEW)
VCC 20 S1 19 Ds7 18 Q7 17 I/O7 I/O5 I/O3 I/O1 16 15 14 13 CP 12 DS0 11 NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package.
1 S0
2 3 4 OE1 OE2 I/O6
8 5 6 7 I/O4 I/O2 I/O0 Q0
9 10 MR GND
LOADING (Note a) PIN NAMES CP DS0 DS7 I/On OE1, OE2 Q0, Q7 MR S0, S1 Clock Pulse (Active Positive-Going Edge) Input Serial Data Input for Right Shift Serial Data Input for Left Shift Parallel Data Input or Parallel Output (3-State) 3-State Output Enable (Active LOW) Inputs Serial Outputs Asynchronous Master Reset (Active LOW) Input Mode Select Inputs HIGH 0.5 U.L. 0.5 U.L. 0.5 U.L. 0.5 U.L. 65 U.L. 0.5 U.L. 10 U.L. 0.5 U.L. 1 U.L. LOW 0.25 U.L. 0.25 U.L. 0.25 U.L. 0.25 U.L. 15 U.L. 0.25 U.L. 5 U.L. 0.25 U.L. 0.5 U.L.
NOTES: a) 1 TTL Unit Load (U.L.) = 40 mA HIGH/1.6 mA LOW.
S1 19 S0
1
LOGIC DIAGRAM
18
DS7 DS0
11
12
CLOCK Q0 MR OE1 OE2
8 9 2 3
D CK CLR Q
D CK CLR Q
D CK CLR Q
D CK CLR Q
D CK CLR Q
D CK CLR Q
D CK CLR Q
D CK CLR Q
17
Q7 VCC = PIN 20 GND = PIN 10 = PIN NUMBERS
7
13
6
14
5
15
4
16
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
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SN74LS299
FUNCTION TABLE
INPUTS MR L L L L L H H H H H H H H S1 X X H L X L L H H H L L L S0 X X H X L H H L L H L L L OE1 H X X L L X L X L X H X L OE2 X H X L L X L X L X X H L X X X CP X X X X X DS0 X X X X X D D X X X X X X DS7 X X X X X X X D D X X X X Asynchronous Reset; Q0 = Q7 = LOW Reset I/O Voltage Undetermined Asynchronous Reset; Q0 = Q7 = LOW I/O Voltage LOW Shift Right; DQ0; Q0 1; etc. Shift Right; DQ0 & I/O0; Q0 1 & I/O1; etc. Shift Left; DQ7; Q7 6; etc. Shift Left; DQ7 & I/O7; Q7 6 & I/O6; etc. Parallel Load; I/On RESPONSE
Q
Q
O
Qn
Q
Hold: I/O Voltage undetermined Hold: I/On = Qn
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial
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SN74LS299
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits Symbol VIH VIL VIK VOH VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage I/O0 - I/O7 Output HIGH Voltage Q 0 , Q7 Output LOW Voltage g I/O0 - I/O7 Output LOW Voltage g I/O0 - I/O7 Output Off Current HIGH I/O0 - I/O7 Output Off Current LOW I/O0 - I/O7 Others S0, S1, I/O0 - I/O7 IIH Input HIGH C I t Current t Others S0, S1 I/O0 - I/O7 Others IIL IOS Input LOW Current S0, S1 Short Circuit Current (Note 1) Power Supply Current Q 0 , Q7 I/O0 - I/O7 - 20 - 30 - 0.8 -100 -130 53 mA mA mA mA 2.4 2.7 - 0.65 3.1 3.4 0.25 0.35 0.4 0.5 0.4 0.5 40 - 400 20 40 0.1 0.2 0.1 - 0.4 Min 2.0 0.8 - 1.5 Typ Max Unit V V V V V V V V V A A A A mA mA mA mA VCC = MAX, VIN = 0 4 V MAX 0.4 VCC = MAX VCC = MAX VCC = MAX VCC = MAX, VIN = 7 0 V MAX 7.0 VCC = MAX, VIN = 5.5 V VCC = MAX, VIN = 2.7 V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for All Inputs VCC = MIN, IIN = - 18 mA VCC = MIN, IOH = MAX VCC = MIN, IOH = MAX IOL = 12 mA IOL = 24 mA IOL = 4.0 mA IOL = 8.0 mA VCC = VCC MIN, VIN = VIL or VIH per Truth Table VCC = VCC MIN, VIN = VIL or VIH per Truth Table
VO OL
VO OL IOZH IOZL
VCC = MAX, VOUT = 2.7 V VCC = MAX, VOUT = 0.4 V
ICC
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
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4
SN74LS299
AC CHARACTERISTICS (TA = 25C, VCC = 5.0 V)
Limits Symbol fMAX tPHL tPLH tPHL tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ Parameter Maximum Clock Frequency Propagation Delay, Clock to Q0 or Q7 Propagation Delay, Clear to Q0 or Q7 Propagation Delay, Clock to I/O0 - I/O7 Propagation Delay, Clear to I/O0 - I/O7 Output Enable Time Output Disable Time Min 25 Typ 35 26 22 27 26 17 26 13 19 10 10 39 33 40 39 25 40 21 30 15 15 Max Unit MHz ns ns ns ns ns ns CL = 5.0 pF CL = 45 pF, RL = 667 CL = 15 pF Test Conditions
AC SETUP REQUIREMENTS (TA = 25C, VCC = 5.0 V)
Limits Symbol tW tW tW ts ts th th trec Parameter Clock Pulse Width HIGH Clock Pulse Width LOW Clear Pulse Width LOW Data Setup Time Select Setup Time Data Hold Time Select Hold Time Recovery Time Min 25 13 20 20 35 0 10 20 Typ Max Unit ns ns ns ns ns ns ns ns VCC = 5 0 V 5.0 Test Conditions
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5
SN74LS299
3-STATE WAVEFORMS
VIN
1.3 V tPLH
1.3 V tPHL 1.3 V
VIN
1.3 V tPLH
1.3 V tPHL 1.3 V
VOUT
1.3 V
VOUT
1.3 V
Figure 1.
Figure 2.
VE 1.5 V VE VOUT tPZL 1.5 V 0.5 V 1.5 V tPLZ 1.5 V VOL
VE 1.5 V VE tPZH 1.5 V VOUT tPHZ 1.5 V VOH 1.5 V 0.5 V
Figure 3.
Figure 4.
AC LOAD CIRCUIT SWITCH POSITIONS
VCC RL SYMBOL tPZH tPZL tPLZ tPHZ SW1 Open Closed Closed Closed SW2 Closed Open Closed Closed
SW1
TO OUTPUT UNDER TEST
5 k CL* SW2
* Includes Jig and Probe Capacitance.
Figure 5.
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6
SN74LS299
PACKAGE DIMENSIONS
N SUFFIX PLASTIC PACKAGE CASE 738-03 ISSUE E
-A-
20 11 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. INCHES MIN MAX 1.010 1.070 0.240 0.260 0.150 0.180 0.015 0.022 0.050 BSC 0.050 0.070 0.100 BSC 0.008 0.015 0.110 0.140 0.300 BSC 0_ 15 _ 0.020 0.040 MILLIMETERS MIN MAX 25.66 27.17 6.10 6.60 3.81 4.57 0.39 0.55 1.27 BSC 1.27 1.77 2.54 BSC 0.21 0.38 2.80 3.55 7.62 BSC 0_ 15_ 0.51 1.01
B
1 10
C
L
-T-
SEATING PLANE
K M E G F D
20 PL
N J 0.25 (0.010)
M 20 PL
0.25 (0.010) TA
M
M
TB
M
DIM A B C D E F G J K L M N
D SUFFIX PLASTIC SOIC PACKAGE CASE 751D-05 ISSUE F
D
A
11 X 45 _
q
NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 12.65 12.95 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_
H
M
B
M
20
10X
0.25
E
1
10
h
20X
B 0.25
M
B TA
S
B
S
A
SEATING PLANE
DIM A A1 B C D E e H h L
L
18X
e
A1
q
T
C
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7
SN74LS299
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
PUBLICATION ORDERING INFORMATION
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8
SN74LS299/D


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